In the fabrication of semiconductor circuits and other chips such as memory chips, many chips are formed in a checker-board fashion on a generally round wafer of semiconductor material. During the assembly process these chips are cut apart and placed on lead-frames or the like, then packaged and tested. To save the cost of packaging defective chips the wafer is tested by a wafer prober before being diced. In the wafer prober, the bonding pads of each chip are brought into contact with a set of test needles which, in turn, are connected to an electronic tester. The functionality of the chip is checked and failed chips are marked with an ink dot. Often, instead of immediately inking the failed chips, a positional map of the wafer is stored in the system memory and is reused and updated in secondary tests or assembly operations.
Most wafer probers include a loader portion and a prober portion. In addition, they are fully automatic and process the wafers in lots of 25 or 50. The wafers are transported in cassettes and placed in a loader portion of the of the prober. A robotic wafer handler transports each wafer sequentially from storage cassettes to a pre-aligner, where the wafer is centered and pre-oriented by locating the flat or other physical marks such as a notch. The wafer is then delivered to a prober stage approximately centered and with the chip checker pattern approximately parallel to the X-Y stage motion. The orientation is coordinated to suit the test needles and chip test pads.
From the time a new wafer is delivered to the prober stage and until it is returned fully tested, the prober and loader portions operate independently. The prober stage first brings the wafer under an alignment unit where the actual chip pattern is detected and accurately aligned to suit the test needle array. Then, each chip is sequentially brought into contact with the probes of the needle array and are functionally checked by the tester. Depending on the testing complexity and wafer size this may take a few minutes to more than hour. The loader operation on the other hand takes less than a minute regardless of chip complexity. A wafer therefore sits idle in the loader for many hours.
The conventional loader provides no detailed information about the chips to the probing control which must calculate the chip position relative to the wafer edge without knowledge of the chip pattern near the edge. Many of the chips along the wafer edge are incomplete and test defective even though the calculation has determined them as physically complete and potentially good. It is a waste of time to test an incomplete chip and an incomplete chip may even cause damage to the sensitive probe needles slipping over the edge. To avoid this, the prober does not put partial edge chips in contact with the needles. However, the inaccurate knowledge of the chip's physical condition may lead to some good chips not being tested and arbitrarily marked defective. To improve this situation a control map is manually generated to steer the prober to the testable chips. Such a control map, however, does not adequately take care of wafer to wafer differences and is itself time consuming to generate.
A chip may have been subjected to damage both before and during probing. When such a chip fails the electrical wafer test it causes inefficiency. But such damage might not affect the chip operation until after the chip has been packaged and installed, consequently, it is not sensed by the electrical wafer test. To prevent such defects which escape detection in the electrical test, the wafers are subjected to visual inspection both pre- and post-probing. In the pre-probe case this is usually done without exact knowledge of chip to chip relation and thus has virtually no value in wafer chip sorting. The post-probe inspection is largely manual as no reliable automatic methods have been found that compares with the electrical probing test. The post-probe inspection is therefore a separate processing step requiring extra wafer lot handling and equipment.
This invention relates to finding visual defects in semiconductor wafers and chips and to sorting out those defective wafers or chips which would cause failure in later applications. One inspection object is semiconductor wafers and the task is to sort out defective chips before they are diced apart. Another inspection object is printed circuit boards (PCB) where it is necessary to visually detect flaws in artwork as well as the finished product. Common to both fields is the goal of maximizing the output of long term "good products" and eliminate the passage of potentially "defective products" which can cause serious economic consequences in later assemblies.